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8-bit touch key flash mcu bs83b08-3/bs83b12-3 bs83b16-3/bs83b16g-3 BS83C24-3 revision: 1.30 date: september 22, 2011
table of contents technical document ...........................................................................6 features ...............................................................................................6 cpu features ........................................................................................................6 peripheral features ................................................................................................6 general description ............................................................................7 selection table ....................................................................................7 block diagram .....................................................................................8 pin description ....................................................................................9 bs83b08-3/b12-3/b16-3 ........................................................................................9 BS83C24-3 ...........................................................................................................10 pad assignment for bs83b16g-3 ....................................................11 pad coordinates for bs83b16g-3....................................................11 absolute maximum ratings .............................................................12 d.c. characteristics ..........................................................................12 a.c. characteristics ..........................................................................13 power-on reset characteristics ......................................................14 oscillator temperature/frequency characteristics .......................15 system architecture .........................................................................18 clocking and pipelining ........................................................................................18 program counter ..................................................................................................19 stack ....................................................................................................................19 arithmetic and logic unit alu ...........................................................................20 flash program memory ....................................................................20 structure ...............................................................................................................20 special vectors .....................................................................................................21 look-up table .......................................................................................................21 table program example .....................................................................................22 in circuit programming .........................................................................................23 ram data memory.............................................................................24 structure ...............................................................................................................24 special function register description ...........................................24 indirect addressing registers iar0, iar1 ..........................................................24 rev. 1.30 2 september 22, 2011 contents
memory pointers mp0, mp1 ..............................................................................28 bank pointer bp ................................................................................................28 accumulator acc ..............................................................................................29 program counter low register pcl..................................................................29 look-up table registers tblp, tbhp, tblh .....................................................29 status register status ...................................................................................30 eeprom data memory .....................................................................31 eeprom data memory structure ........................................................................31 reading data from the eeprom .........................................................................34 writing data to the eeprom ...............................................................................34 write protection ....................................................................................................34 eeprom interrupt ...............................................................................................34 programming considerations ...............................................................................35 programming examples .......................................................................................35 oscillator............................................................................................36 oscillator overview ...............................................................................................36 system clock configurations ................................................................................36 internal high speed rc oscillator hirc ............................................................36 internal low speed rc oscillator lirc .............................................................37 operating modes and system clocks .............................................38 system clocks ......................................................................................................38 control register ...................................................................................................39 system operation modes .....................................................................................40 operating mode switching ....................................................................................41 normal mode to slow mode switching ...........................................................42 slow mode to normal mode switching ...........................................................42 entering the sleep mode ....................................................................................42 entering the idle0 mode .....................................................................................43 entering the idle1 mode .....................................................................................43 standby current considerations ...........................................................................43 wake-up ...............................................................................................................44 programming considerations ...............................................................................44 watchdog timer ................................................................................45 watchdog timer clock source .............................................................................45 watchdog timer control register .........................................................................45 watchdog timer operation ...................................................................................45 reset and initialisation .....................................................................47 reset functions ...................................................................................................47 reset initial conditions .........................................................................................50 input/output ports.............................................................................60 i/o register list ....................................................................................................60 contents rev. 1.30 3 september 22, 2011
pull-high resistors ................................................................................................62 port a wake-up ....................................................................................................63 i/o port control register ......................................................................................64 i/o pin structures .................................................................................................66 programming considerations ...............................................................................66 timer/event counters .......................................................................67 configuring the timer/event counter input clock source .....................................68 timer register tmr, tmr0, tmr1l, tmr1h ...................................................68 timer control register tmrc, tmr0c, tmr1c ...............................................68 8-bit timer/event counter operating mode ..........................................................70 16-bit timer/event counter 1 operating modes -- BS83C24-3 .............................70 prescaler ..............................................................................................................73 pfd function .......................................................................................................73 i/o interfacing .......................................................................................................73 programming considerations ...............................................................................73 timer program example-timer/event counter 0 ..................................................74 touch key function ..........................................................................75 touch key structure .............................................................................................75 touch key register definition ...............................................................................76 touch key operation ............................................................................................79 touch key interrupt ..............................................................................................80 programming considerations ...............................................................................80 serial interface module sim...........................................................81 spi interface .........................................................................................................81 i 2 c interface .........................................................................................................87 interrupts............................................................................................96 interrupt registers ................................................................................................96 interrupt register contents ...................................................................................97 interrupt operation .............................................................................................104 external interrupt ................................................................................................107 multi-function interrupt ........................................................................................107 time base interrupts ..........................................................................................108 timer/event counter interrupt ............................................................................109 eeprom interrupt .............................................................................................109 touch key interrupts ...........................................................................................109 sim interrupt .......................................................................................................109 interrupt wake-up function .................................................................................110 programming considerations .............................................................................110 application circuits.........................................................................111 instruction set .................................................................................112 introduction .........................................................................................................112 instruction timing ................................................................................................112 rev. 1.30 4 september 22, 2011 contents
moving and transferring data .............................................................................112 arithmetic operations .........................................................................................112 logical and rotate operations ............................................................................112 branches and control transfer ...........................................................................113 bit operations .....................................................................................................113 table read operations .......................................................................................113 other operations ................................................................................................113 instruction set summary .....................................................................................114 instruction definition ......................................................................116 package information .......................................................................126 16-pin nsop (150mil) outline dimensions .........................................................126 16-pin ssop (150mil) outline dimensions .........................................................127 20-pin sop (300mil) outline dimensions ............................................................128 20-pin ssop (150mil) outline dimensions .........................................................129 24-pin sop (300mil) outline dimensions ............................................................130 24-pin ssop (150mil) outline dimensions .........................................................131 28-pin sop (300mil) outline dimensions ............................................................132 28-pin ssop (150mil) outline dimensions .........................................................133 44-pin qfp (10mm 10mm) outline dimensions ................................................134 reel dimensions ................................................................................................135 carrier tape dimensions ....................................................................................136 contents rev. 1.30 5 september 22, 2011
technical document application note ha0075e mcu reset and oscillator circuits application note features cpu features operating voltage: f sys = 8mhz: v lvr ~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 16mhz: 4.5v~5.5v fully integrated 8/12/16/24 touch key functions -- require no external components power down and wake-up functions to reduce power consumption fully integrated low and high speed internal oscillators low speed -- 32khz high speed -- 8mhz, 12mhz, 16mhz multi-mode operation: normal, slow, idle and sleep all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 8 subroutine nesting levels bit manipulation instruction peripheral features flash program memory: up to 4k 16 ram data memory: 160 8 ~ 512 8 eeprom memory: up to 128 8 watchdog timer function up to 41 bidirectional i/o lines external interrupt line shared with i/o pin single 8-bit timer/event counter single 16-bit timer/event counter for BS83C24-3 single time-base functions for generation of fixed time interrupt signals i 2 c and spi interfaces low voltage reset function 8/12/16/24 touch key functions rev. 1.30 6 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
general description these devices are a series of flash memory type 8-bit high performance risc architecture microcontrollers with fully integrated touch key functions. with all touch key functions provided internally and with the convenience of flash memory multi-programming features, this device range has all the features to offer designers a reliable and easy means of implementing touch keyes within their products applications. the touch key functions are fully integrated completely eliminating the need for external components. in addition to the flash program memory, other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. protective features such as an internal watchdog timer and low voltage reset functions coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. all devices include fully integrated low and high speed oscillators which require no external components for their implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. easy communication with the outside world is provided using the internal i 2 c and spi interfaces, while the inclusion of flexible i/o programming features, timer/event counters and many other features further enhance device functionality and flexibility. these touch key devices will find excellent use in a huge range of modern touch key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few. selection table most features are common to all devices, the main distinguishing feature is the number of i/os and touch keys. the following table summarises the main features of each device. part no. internal clock vdd system clock program memory data memory data eeprom i/o 8-bit timer 16-bit timer touch key spi/ i 2 c pfd stack package bs83b08-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz~ 16mhz 2k 15 160 864 8131 81 4 16nsop 16ssop bs83b12-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz~ 16mhz 2k 15 288 864 8171 12 1 4 20sop 20ssop bs83b16-3 bs83b16g-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz~ 16mhz 2k 15 288 864 8211 16 1 4 24sop 24ssop cog BS83C24-3 8mhz 12mhz 16mhz v lvr ~ 5.5v 8mhz~ 16mhz 4k 16 512 8 128 841 1 1 2411 8 28sop 28ssop 44qfp bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 7 september 22, 2011
block diagram pin assignment rev. 1.30 8 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu

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+ ( ( + ( 6 , 1 2 4 ( . , 1 2 3 ( 5 , 1 2 2 ( 4 , 1 2 - ( 3 , 1 2 0 ( 2 , 1 - 8
pin description the function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. bs83b08-3/b12-3/b16-3/b16g-3 pin name function opt i/t o/t description pa0/sdi/sda pa0 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdi simc0 st spi data input sda simc0 st nmos i 2 c data pa1/sdo pa1 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdo simc0 cmos spi data output pa2/sck/scl pa2 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock pa3/scs pa3 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. scs simc0 st cmos spi slave select pa4/int pa4 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. int integ st external interrupt pb0/key1~ pb3/key4 pb0~pb3 pbpu st cmos general purpose i/o. register enabled pull-up. key1~key4 tkm0c1 nsi touch key inputs pb4/key5~ pb7/key8 pb4~pb7 pbpu st cmos general purpose i/o. register enabled pull-up. key5~key8 tkm1c1 nsi touch key inputs pc0/key9~ pc3/key12 pc0~pc3 pcpu st cmos general purpose i/o. register enabled pull-up. key9~key12 tkm2c1 nsi touch key inputs pc4/key13~ pc7/key16 pc4~pc7 pcpu st cmos general purpose i/o. register enabled pull-up. key13~key16 tkm3c1 nsi touch key inputs res reset pin st vdd power supply * pwr vss ground ** pwr note: i/t: input type o/t: output type opt: optional by register selection pwr: power st: schmitt trigger input cmos: cmos output nmos: nmos output nsi; non-standard input bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 9 september 22, 2011
BS83C24-3 pin name function opt i/t o/t description pa0/sdi/sda pa0 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdi simc0 st spi data input sda simc0 st nmos i 2 c data pa1/sdo pa1 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sdo simc0 cmos spi data output pa2/sck/scl pa2 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. sck simc0 st cmos spi serial clock scl simc0 st nmos i 2 c clock pa3/scs pa3 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. scs simc0 st cmos spi slave select pa4/int pa4 pawu papu st cmos general purpose i/o. register enabled pull-up and wake-up. int integ st external interrupt res reset pin st pb0/key1~ pb3/key4 pb0~pb3 pbpu st cmos general purpose i/o. register enabled pull-up. key1~key4 tkm0c1 nsi touch key inputs pb4/key5~ pb7/key8 pb4~pb7 pbpu st cmos general purpose i/o. register enabled pull-up. key5~key8 tkm1c1 nsi touch key inputs pc0/key9~ pc3/key12 pc0~pc3 pcpu st cmos general purpose i/o. register enabled pull-up. key9~key12 tkm2c1 nsi touch key inputs pc4/key13~ pc7/key16 pc4~pc7 pcpu st cmos general purpose i/o. register enabled pull-up. key13~key16 tkm3c1 nsi touch key inputs pd0/key17~ pd3/key20 pd0~pd3 pdpu st cmos general purpose i/o. register enabled pull-up. key17~key20 tkm4c1 nsi touch key inputs pd4/key21~ pd7/key24 pd4~pd7 pdpu st cmos general purpose i/o. register enabled pull-up. key21~key24 tkm5c1 nsi touch key inputs pe0/pfd pe0 pepu st cmos general purpose i/o. register enabled pull-up. pfd tmr1c cmos pfd output pe1~pe7 pe1~pe7 pepu st cmos general purpose i/o. register enabled pull-up. pf0/tc1 pf0 pfpu st cmos general purpose i/o. register enabled pull-up. tc1 st external timer 1 clock input pf1~pf3 pf1~pf3 pfpu st cmos general purpose i/o. register enabled pull-up. vdd vdd pwr power supply vss vss pwr ground note: i/t: input type; o/t: output type opt: optional by register selection pwr: power; st: schmitt trigger input sp: special input; cmos: cmos output; nmos: nmos output nsi; non-standard input rev. 1.30 10 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
pad assignment for bs83b16g-3 pad coordinates for bs83b16g-3 pad no. pad name x y pad no. pad name x y 1 dummy -1361.480 677.500 20 dummy 1007.340 677.500 2 align1 -1379.250 -557.780 21 dummy 927.340 677.500 3 dummy2020 -1335.090 -658.000 22 dummy 847.340 677.500 4 vss -1240.090 -658.000 23 pb0/key1 585.120 677.500 5 vss -1145.090 -658.000 24 pb1/key2 462.1220 677.500 6 vdd -1050.090 -658.000 25 pb2/key3 339.120 677.500 7 vdd -955.090 -658.000 26 pb3/key4 216.120 677.500 8 res 771.020 -658.000 27 pb4/key5 93.120 677.500 9 pa2/sck/scl 866.020 -658.000 28 pb5/key6 -29.880 677.500 10 pa0/sdi/sda 961.020 -658.000 29 pb6/key7 -152.880 677.500 11 pa3/scs 1056.020 -658.000 30 pb7/key8 -275.880 677.500 12 pa4/int 1151.020 -658.000 31 pc0/key9 -398.880 677.500 13 pa1/sdo 1246.020 -658.000 32 pc1/key10 -521.880 677.500 14 dummy 1341.020 -658.000 33 pc2/key11 -644.880 677.500 15 align2 1361.400 -559.990 34 pc3/key12 -767.880 677.500 16 dummy 1327.340 677.500 35 pc4/key13 -890.880 677.500 17 dummy 1247.340 677.500 36 pc5/key14 -1013.880 677.500 18 dummy 1167.340 677.500 37 pc6/key15 -1136.880 677.500 19 dummy 1087.340 677.500 38 pc7/key16 -1259.880 677.500 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 11 september 22, 2011 - 2 3 4 5 . 6 8 - 0 - - - 2 - 3 - 4 - 5 - .- 6 - - 82 02 -2 2 2 32 42 52 .2 62 2 83 03 -3 23 33 43 5 3 .3 6 3
absolute maximum ratings supply voltage ...............................................................................................v ss 0.3v to v ss +6.0v storage temperature ................................................................................................. 50 cto125 c input voltage .................................................................................................v ss 0.3v to v dd +0.3v operating temperature .................................................................................................. 40 cto85 ci ol total .......................................................................................................................... ........80ma i oh total .................................................................................................................................. 80ma total power dissipation .........................................................................................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum rat - ings may cause substantial damage to the device. functional operation of this device at other condi - tions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hirc) f sys =8mhz v lvr 5.5 v f sys =12mhz 2.7 5.5 v f sys =16mhz 4.5 5.5 v i dd1 operating current (hirc), (f sys =f h ) 3v no load, f h =8mhz, wdt enable 1.2 1.8 ma 5v 2.2 3.3 ma 3v no load, f h =12mhz, wdt enable 1.6 2.4 ma 5v 3.3 5.0 ma 5v no load, f h =16mhz, wdt enable 4.0 6.0 ma i dd2 operating current (lirc), (f sys =f l ) for bs83b08-3/b12-3/b16-3 3v no load, f l =32khz, wdt enable 50 100 a 5v 70 150 a i dd3 operating current (lirc), (f sys =f l ) for BS83C24-3 3v no load, f l =32khz, wdt enable 15 30 a 5v 30 60 a i idle0 idle0 mode standby current 3v no load, lvr disable 1.5 3.0 a 5v 3.0 6.0 a i idle1 idle1 mode standby current 3v no load, lvr disable, f sys =12mhz on 0.9 1.4 ma 5v 1.6 2.4 ma i sleep sleep1 mode standby current 3v no load, lvr disable 1.5 3.0 a 5v 2.5 5.0 a v il1 input low voltage for i/o ports or input pins except res pin 5v 0 1.5 v 0 0.2v dd v v ih1 input high voltage for i/o ports or input pins except res pin 5v 3.5 5.0 v 0.8v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v rev. 1.30 12 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
symbol parameter test conditions min. typ. max. unit v dd conditions v lvr lvr voltage level lvr enable 5% 2.55 +5% v v ol output low voltage i/o port 3v i ol =9ma 0.3 v 5v i ol =20ma 0.5 v v oh output high voltage i/o port 3v i oh =3.2ma 2.7 v 5v i oh =7.4ma 4.5 v r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating clock v lvr ~5.5v dc 8 mhz 2.7v~5.5v dc 12 mhz 4.5v~5.5v dc 16 mhz f hirc system clock (hirc) 3v/5v ta=25c 2% 8 +2% mhz 3v/5v ta=25c 2% 12 +2% mhz 5v ta=25c 2% 16 +2% mhz 3v/5v ta=0~70c 4% 8 +3% mhz 3v/5v ta=0~70c 4% 12 +3% mhz 5v ta=0~70c 4% 16 +3% mhz 2.5v~ 4.0v ta=0~70c 9% 8 +6% mhz 3.0v~ 5.5v ta=0~70c 5% 8 +12% mhz 2.7v~ 4.0v ta=0~70c 9% 12 +5% mhz 3.0v~ 5.5v ta=0~70c 5% 12 +11% mhz 4.5v~ 5.5v ta=0~70c 5% 16 +5% mhz 2.5v~ 4.0v ta= 40c~85c 12% 8 +6% mhz 3.0v~ 5.5v ta= 40 c~85c 8% 8 +12% mhz 2.7v~ 4.0v ta= 40c~85c 13% 12 +5% mhz 3.0v~ 5.5v ta= 40c~85c 8% 12 +11% mhz 4.5v~ 5.5v ta= 40c~85c 7% 16 +5% mhz bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 13 september 22, 2011 ta=25 c
symbol parameter test conditions min. typ. max. unit v dd conditions f lirc system clock (lirc) 5v 10% 32 +10% khz 2.2v~ 5.5v ta=40c~+85c 50% 32 +60% khz f timer timer input pin frequency 1 f sys t res external reset low pulse width 1 s t int interrupt pulse width 1 s t lvr low voltage width to reset 60 120 240 s t eerd eeprom read time 24 t sys t eewr eeprom write time 24ms t sst system start-up timer period (wake-up from halt) f sys =hirc 15~16 t sys f sys =lirc 1~2 note: 1. t sys =1/f sys 2. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv r por ac vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms rev. 1.30 14 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu + ( ( +

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oscillator temperature/frequency characteristics the following characteristic graphics depicts typical oscillator behavior. the data presented here is a statistical summary of data gathered on units from different lots over a period of time. this is for information only and the figures were not tested during manufacturing. in some of the graphs, the data exceeding the specified operating range are shown for information purposes only. the device will operate properly only within the specified range. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 15 september 22, 2011 internal rc -- 8mhz (3v) 7.300 7.400 7.500 7.600 7.700 7.800 7.900 8.000 8.100 8.200 8.300 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 2.5v 2.7v 3.0v 4.0v internal rc -- 8mhz (5v) 7.400 7.600 7.800 8.000 8.200 8.400 8.600 8.800 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 3.0v 4.0v 4.5v 4.75v 5.0v 5.25v 5.5v % 9 : % 9 :
rev. 1.30 16 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu internal rc -- 12mhz (3v) 10.800 11.000 11.200 11.400 11.600 11.800 12.000 12.200 12.400 -60 -40 -20 0 20 40 60 80 100 120 140 ta (c) f sys (mhz) 2.7v 3.0v 4.0v internal rc -- 12mhz (5v) 11.400 11.600 11.800 12.000 12.200 12.400 12.600 12.800 13.000 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 3.0v 4.0v 4.5v 4.75v 5.0v 5.25v 5.5v % 9 : % 9 :
bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 17 september 22, 2011 internal rc -- 16mhz (5v) 15.300 15.400 15.500 15.600 15.700 15.800 15.900 16.000 16.100 16.200 16.300 16.400 -60 -40 -20 0 20 40 60 80 100 120 140 ta(c) f sys (mhz) 4.5v 4.75v 5.0v 5.25v 5.5v % 9 :
system architecture a key factor in the high-performance features of the holtek range of microcontroller is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontroller providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a high or low speed oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. rev. 1.30 18 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu % ; % 9 : < % ; % 9 - : % ; % 9 = - : < % ; % 9 : % ; % 9 = 2 : < % ; % 9 = - : = - = 2 > 1 9 % ' : % ' % - % % ' % 2 % ' % 3 % ' % 4 " system clocking and pipelining % ; % - < % ; % - % ; % 2 % " - 2 3 4 5 . ( # ) 1 ? + % ) @ a - 2 & b ) # # % ( # ) 1 # % a - 2 & b ? ? 7 < % ; % 2 % ; % 3 % ; % . < % ; % . % ; % 6 instruction fetching
for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register bs83b08-3 bs83b12-3 bs83b16-3 bs83b16g-3 pc10~pc8 pcl7~pcl0 BS83C24-3 pc11~pc8 the lower byte of the program counter, known as the program counter low register or pcl, is avail- able for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 19 september 22, 2011
if the stack is overflow, the first program counter save in the stack will be lost. device stack levels bs83b08-3 bs83b12-3 bs83b16-3 bs83b16g-3 4 BS83C24-3 8 arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, these flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. structure the program memory has a capacity of 2k 15 or 4k 16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. device capacity bs83b08-3 bs83b12-3 bs83b16-3 bs83b16g-3 2k15 BS83C24-3 4k16 rev. 1.30 20 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu % ' % # / % - ' % # / % 2 ' % # / % " % > % ' ' * % > % ' 0 0 0 4 & 0 0 2 0 & " + - 5 % 0 6 & 0 0 0 0 &
0 0 0 4 & 0 0 2 & " + - . % 0 & 0 0 0 0 &
flash program memory structure
special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers define the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0 . the accompanying diagram illustrates the addressing data flow of the look-up table. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 21 september 22, 2011
% * # & ! %
& % * # $ % * * # %
( ) - 5 % % - . %
# % " % * & %
instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: pc11~pc8: current program counter bits @7~@0: table pointer tblp bits for the bs83b08-3, bs83b12-3 and bs83b16-3/bs83b16g-3, the table address location is 11 bits, i.e. from b10~b0. for the BS83C24-3, the table address location is 12 bits, i.e. from b11~b0
table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at ; program memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at ; program memory address 705h transferred to tempreg2 and tblh in ; this example the data 1ah is transferred to tempreg1 and data ; 0fh to register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : rev. 1.30 22 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to writer programming pin correspondence table is as follows: holtek writer pin name pin description icpda pa0 serial address and data -- read/write icpck pa2 address and data serial clock input icpms res programming mode select vdd vdd power supply (5.0v) vss vss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the res pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the pa0 and pa2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 23 september 22, 2011 + ( ( ( ) , + % % ) 0 ) 2 +
+ ( ( % ! % c c c note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf.
ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the first of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. device capacity bank 0 bank 1 bank 2 bank 3 bs83b08-3 1608 60h~ffh bs83b12-3 2888 60h~ffh 80h~ffh bs83b16-3 bs83b16g-3 2888 60h~ffh 80h~ffh BS83C24-3 5128 80h~ffh 80h~ffh 80h~ffh 80h~ffh general purpose data memory the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into several banks for the devices. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. rev. 1.30 24 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
note: the reserved bytes shown in the table must not be modified by the user. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 25 september 22, 2011 0 0 & 0 - & 0 2 & 0 3 & 0 4 & 0 5 & 0 . & 0 6 & 0 & 0 8 & 0 ) & 0 * & 0 & 0 ( & 0 & 0 & - 0 & - - & - 2 & - 3 & - 4 & - 5 & - . & - 6 & - & - 8 & - ) & - * & - & - ( & - & - & 2 0 & 2 - & 2 2 & 2 3 & 2 4 & 2 5 & 2 . & 2 6 & 2 & 2 8 & 2 ) & 2 * & 2 & 2 ( & 2 & 2 & 3 0 & 3 - & 3 2 & 3 3 & 3 4 & 3 5 & 3 . & 3 6 & 3 & 3 8 & 3 ) & 3 * & 3 & 3 ( & 3 & 3 & 4 0 & 4 - & 4 2 & 4 3 & 4 4 & 4 5 & 4 . & 4 6 & 4 & 4 8 & 4 ) & 4 * & 4 & 4 ( & 4 & 4 & 5 0 & 5 - & 5 2 & 5 3 & 5 4 & 5 5 & 5 . & 5 6 & 5 & 5 8 & 5 ) & 5 * & 5 & 5 ( & 5 & 5 &

, - - . ( & , - - . ( #
/
/ , - 0 , - - , - 2 , - 3 ! ! ! ! !
# ! ! ! % % % % % % % % % ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! )
0 0 )
- - * ) # * # * # & * & ) ! ( ! 7 d 7 0 7 - 7 2 0 ! ! ) ) ) ! ) ! ! ! ( *

) ( * * * ! 2 0 - ( ) 2 , 0 - . ( & , 0 - . ( #
/
/ , 0 0 , 0 - , 0 2 , 0 3 0 0 & 0 - & 0 2 & 0 3 & 0 4 & 0 5 & 0 . & 0 6 & 0 & 0 8 & 0 ) & 0 * & 0 & 0 ( & 0 & 0 & - 0 & - - & - 2 & - 3 & - 4 & - 5 & - . & - 6 & - & - 8 & - ) & - * & - & - ( & - & - & 2 0 & 2 - & 2 2 & 2 3 & 2 4 & 2 5 & 2 . & 2 6 & 2 & 2 8 & 2 ) & 2 * & 2 & 2 ( & 2 & 2 & 3 0 & 3 - & 3 2 & 3 3 & 3 4 & 3 5 & 3 . & 3 6 & 3 & 3 8 & 3 ) & 3 * & 3 & 3 ( & 3 & 3 & 4 0 & 4 - & 4 2 & 4 3 & 4 4 & 4 5 & 4 . & 4 6 & 4 & 4 8 & 4 ) & 4 * & 4 & 4 ( & 4 & 4 & 5 0 & 5 - & 5 2 & 5 3 & 5 4 & 5 5 & 5 . & 5 6 & 5 & 5 8 & 5 ) & 5 * & 5 & 5 ( & 5 & 5 &

)
0 0 )
- - * ) # * # * # & * & ) ! ( ! 7 d 7 0 7 - 7 2 0 - ! ) ) ) ! ) ! ! ! ( *

) ( * * * ! 2 0 - ( ) 2 , 0 - . ( & , 0 - . ( #
/
/ , 0 0 , 0 - , 0 2 , 0 3 , - - . ( & , - - . ( #
/
/ , - 0 , - - , - 2 , - 3 ! ! !
# ! ! ! % % % % % % % % % ! ! ! ! ! ! ! , 2 - . ( & , 2 - . ( #
/
/ , 2 0 , 2 - , 2 2 , 2 3 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! special purpose data memory bs83b08-3/bs83b12-3
note: the reserved bytes shown in the table must not be modified by the user. rev. 1.30 26 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu 0 0 & 0 - & 0 2 & 0 3 & 0 4 & 0 5 & 0 . & 0 6 & 0 & 0 8 & 0 ) & 0 * & 0 & 0 ( & 0 & 0 & - 0 & - - & - 2 & - 3 & - 4 & - 5 & - . & - 6 & - & - 8 & - ) & - * & - & - ( & - & - & 2 0 & 2 - & 2 2 & 2 3 & 2 4 & 2 5 & 2 . & 2 6 & 2 & 2 8 & 2 ) & 2 * & 2 & 2 ( & 2 & 2 & 3 0 & 3 - & 3 2 & 3 3 & 3 4 & 3 5 & 3 . & 3 6 & 3 & 3 8 & 3 ) & 3 * & 3 & 3 ( & 3 & 3 & 4 0 & 4 - & 4 2 & 4 3 & 4 4 & 4 5 & 4 . & 4 6 & 4 & 4 8 & 4 ) & 4 * & 4 & 4 ( & 4 & 4 & 5 0 & 5 - & 5 2 & 5 3 & 5 4 & 5 5 & 5 . & 5 6 & 5 & 5 8 & 5 ) & 5 * & 5 & 5 ( & 5 & 5 &

, - - . ( & , - - . ( #
/
/ , - 0 , - - , - 2 , - 3 ! ! !
# ! ! ! % % % % % % % % % ! ! ! ! ! ! ! , 2 - . ( & , 2 - . ( #
/
/ , 2 0 , 2 - , 2 2 , 2 3 , 3 - . ( & , 3 - . ( #
/
/ , 3 0 , 3 - , 3 2 , 3 3 ! ! ! ! ! ! ! ! )
0 0 )
- - * ) # * # * # & * & ) ! ( ! 7 d 7 0 7 - 7 2 0 - ! ) ) ) ! ) ! ! ! ( *

) ( * * * ! 2 0 - ( ) 2 , 0 - . ( & , 0 - . ( #
/
/ , 0 0 , 0 - , 0 2 , 0 3 special purpose data memory bs83b16-3/bs83b16g-3
note: the reserved bytes shown in the table must not be modified by the user. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 27 september 22, 2011 0 0 & 0 - & 0 2 & 0 3 & 0 4 & 0 5 & 0 . & 0 6 & 0 & 0 8 & 0 ) & 0 * & 0 & 0 ( & 0 & 0 & - 0 & - - & - 2 & - 3 & - 4 & - 5 & - . & - 6 & - & - 8 & - ) & - * & - & - ( & - & - & 2 0 & 2 - & 2 2 & 2 3 & 2 4 & 2 5 & 2 . & 2 6 & 2 & 2 8 & 2 ) & 2 * & 2 & 2 ( & 2 & 2 & 3 0 & 3 - & 3 2 & 3 3 & 3 4 & 3 5 & 3 . & 3 6 & 3 & 3 8 & 3 ) & 3 * & 3 & 3 ( & 3 & 3 & 4 0 & 4 - & 4 2 & 4 3 & 4 4 & 4 5 & 4 . & 4 6 & 4 & 4 8 & 4 ) & 4 * & 4 & 4 ( & 4 & 4 & 5 0 & 5 - & 5 2 & 5 3 & 5 4 & 5 5 & 5 . & 5 6 & 5 & 5 8 & 5 ) & 5 * & 5 & 5 ( & 5 & 5 &

, - - . ( & , - - . ( #
/
/ , - 0 , - - , - 2 , - 3 ! ! !
# ! ! ! % % % % % % % % % ( ( ( ! ! ! , 2 - . ( & , 2 - . ( #
/
/ , 2 0 , 2 - , 2 2 , 2 3 , 3 - . ( & , 3 - . ( #
/
/ , 3 0 , 3 - , 3 2 , 3 3 , 4 - . ( & , 4 - . ( #
/
/ , 4 0 , 4 - , 4 2 , 4 3 )
0 0 )
- - * ) # * # * # & * & ) ! ( 7 3 7 d 7 0 7 - 7 2 0 - 2 ) ) ) ! ) ! ! ! ( *
0
0 ) ( * * * ! 2 0 - ( ) 2 , 0 - . ( & , 0 - . ( #
/
/ , 0 0 , 0 - , 0 2 , 0 3 . 0 & . - & . 2 & . 3 & . 4 & . 5 & . . & . 6 & . & . 8 & . ) & . * & . & . ( & . & . & 6 0 & 6 - & 6 2 & 6 3 & 6 4 & 6 5 & 6 . & 6 6 & 6 & 6 8 & 6 ) & 6 * & 6 & 6 ( & 6 & 6 &

, 5 - . ( & , 5 - . ( #
/
/ , 5 0 , 5 - , 5 2 , 5 3 !
- &
- #
- ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! special purpose data memory BS83C24-3 . 0 & & . 0 & & * ' % 0 * ' % 0 * ' % - 0 & & 0 & & * ' % 0 * ' % - 0 & & * ' % 2 * ' % 3 general purpose data memory
memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. note that for this series of devices, the memory pointers, mp0 and mp1, are both 8-bit registers and used to access the data memory together with their corresponding indirect addressing registers iar0 and iar1. the following example shows how to clear a section of four data memory locations already defined as locations adres1 to adres4. indirect addressing program example data .section
data
adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0
code
org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. bank pointer bp for this series of devices, the data memory is divided into several banks. selecting the required data memory area is achieved using the bank pointer. in the bs83b08-3, bs83b12-3, bs83b16-3 and bs83b16g-3, the data memory is divided into two banks .the bit 0 is used to select data memory banks 0~1. in the BS83C24-3, the data memory is divided into four banks. the bit 0 and bit 1 are used to select data memory banks 0~3. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. rev. 1.30 28 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
bank pointer register -- bs83b08-3, bs83b12-3, bs83b16-3 and bs83b16g-3 b i t76543210 name dmbp0 r/w r/w por 0 bit7~1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 bank pointer register -- BS83C24-3 b i t76543210 name dmbp1 dmbp0 r/w r/w r/w por 00 bit7~1 unimplemented, read as 0 bit 0 dmbp1~dmbp0 : select data memory banks 0: bank 0 1: bank 1 2: bank 2 3: bank 3 accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specified program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defined location. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 29 september 22, 2011
status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, operations related to the status register may give different results due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register b i t76543210 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 00xxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero rev. 1.30 30 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
bit 1 ac : auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. eeprom data memory the device contains an area of internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64 8or128 8 bits for this series of devices. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address bs83b08-3/b12-3/b16-3/b16g-3 648 00h ~ 3fh BS83C24-3 1288 00h ~ 7fh eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must first be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 31 september 22, 2011
bs83b08-3/b12-3/b16-3/b16g-3 eeprom register list name bit 76543210 eea d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eea register b i t76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por xxxxxx x unknown bit 7~6 unimplemented, read as 0 bit 5~0 data eeprom address data eeprom address bit 5~bit 0 BS83C24-3 eeprom register list name bit 76543210 eea d6 d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eea register b i t76543210 name d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por xxxxxxx x unknown bit 7 unimplemented, read as 0 bit 6~0 data eeprom address data eeprom address bit 6~bit 0 rev. 1.30 32 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
eec register b i t76543210 name wren wr rden rd r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has finished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has finished. setting this bit high will have no effect if the wren has not first been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has finished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has finished. setting this bit high will have no effect if the rden has not first been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. eed register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown bit 7~0 data eeprom data data eeprom data bit 7~bit 0 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 33 september 22, 2011
reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must first be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom the eeprom address of the data to be written must first be placed in the eea register and the data placed in the eed register. to write data to the eeprom, the write enable bit, wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has finished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request flag will both be set. if the global, eeprom and multi-function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt flag will be automatically reset, the eeprom interrupt flag must be manually reset by the application program. more details can be obtained in the interrupt section. rev. 1.30 34 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples reading data from the eeprom polling method mov a, eeprom_adres ; user defined address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eedata ; move read data to register mov read_data, a writing data to the eeprom polling method clr emi mov a, eeprom_adres ; user defined address mov , a mov a, eeprom_data ; user defined data mov , a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit - executed immediately ; after set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write bp bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 35 september 22, 2011
oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of configuration options and registers. oscillator overview the devices include two internal oscillators, a low speed oscillator and high speed oscillator. both can be chosen as the clock source for the main system clock however the slow speed oscillator is also used as a clock source for other functions such as the watchdog timer, time base and timer/event counter. both oscillators require no external components for their implementation. all oscillator options are selected using registers. the high speed oscillator provides higher performance but carries with it the disadvantage of higher power requirements, while the opposite is of course true for the low speed oscillator. with the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimise the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. internal high speed hirc 8, 12 or 16mhz internal low speed lirc 32khz oscillator types system clock configurations there are two methods of generating the system clock, a high speed internal clock source and low speed internal clock source. the high speed oscillator is an internal 8mhz, 12mhz or 16mhz rc oscillator while the low speed oscillator is an internal 32khz rc oscillator. both oscillators are fully integrated and do not require external components. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register allowing the system clock to be dynamically selected. internal high speed rc oscillator hirc the internal high speed rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a power on default frequency of 8 mhz but can be selected to be either 8mhz, 12mhz or 16mhz using the hircs1 and hircs0 bits in the ctrl register. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. rev. 1.30 36 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
ctrl register b i t76543210 name resbf hircs1 hircs0 r/w r/w r/w r/w por x 00 x unknown bit 7 resbf : reset pin reset flag described elsewhere bit 6 unimplemented, read as 0 bits 5,4 hircs1, hircs0 : high frequency clock select 00: 8mhz 01: 16mhz 10: 12mhz 11: 8mhz bits 3,2 unimplemented, read as 0 bits 1,0 reserved bits, must not be modified. internal low speed rc oscillator lirc the internal 32khz system oscillator is the low frequency oscillator. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. after power on this lirc oscillator will be permanently enabled; there is no provision to disable the oscillator using register bits. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 37 september 22, 2011
operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. both the high and low speed system clocks are sourced from internal rc oscillators. rev. 1.30 38 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu # % * % ' % % % % &
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control register a single register, smod, is used for overall control of the internal clocks within the device. smod register b i t76543210 name cks2 cks1 cks0 d4 lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 00000011 bit 7~5 cks2~cks0 : the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which is lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 undefined bit this bit can be read or written by user software program. bit 3 lto : low speed system oscillator ready flag 0: not ready 1: ready this is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset. bit 2 hto : high speed system oscillator ready flag 0: not ready 1: ready this is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. this flag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this flag will always be read as 1 by the application program after device power-on. the flag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 39 september 22, 2011
system operation modes there are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f lirc f tbc normal mode on f h ~f h /64 on on slow mode on f l on on idle0 mode off off on on idle1 mode off on on on sleep mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. the high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with the slow speed clock source. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the high speed clock is off. sleep mode the sleep mode is entered when a halt instruction is executed and when the idlen bit in the smod register is low. in the sleep mode the cpu will be stopped however as the f lirc oscillator continues to run the watchdog timer will continue to operate. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is low. in the idle0 mode the system oscillator the system oscillator will be stopped and will therefore be inhibited from driving the cpu. idle1 mode the idle1 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator. rev. 1.30 40 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f hirc , to the clock source, f hirc /2~f hirc /64 or f lirc . if the clock is from f hirc , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f hirc /16 and f hirc /64 internal clock sources will also stop running. the accompanying flowchart shows what happens when the device moves between the various operating modes. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 41 september 22, 2011 ! " > 1 h > & f > & . 4 > & % ! % > 1 % > #
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normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode clock is sourced from the lirc oscillator. slow mode to normal mode switching in slow mode the system uses the lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0 , but cks2~cks0 is set to 010 , 011 , 100 , 101 , 110 or 111 .asa certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 . when this instruction is executed under the conditions described above, the following will occur: the system clock will be stopped and the application program will stop at the halt instruction, but the f lirc clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. rev. 1.30 42 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu # % # % ( # 0 % ( # - % 7
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entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 0 . when this instruction is executed under the conditions described above, the following will occur: the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f lirc clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 1 . when this instruction is executed under the with conditions described above, the following will occur: the system clock and f lirc clock will be on and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 43 september 22, 2011
wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. system oscillator wake-up time (sleep mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hirc 15~16 hirc cycles 1~2 hirc cycles lirc 1~2 lirc cycles 1~2 lirc cycles wake-up times programming considerations the high speed and low speed oscillators both use the same sst counter. for example, if the system is woken up from the sleep mode the hirc oscillator needs to start-up from an off state. if the device is woken up from the sleep mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute the first instruction after hto is high. rev. 1.30 44 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal low speed oscillator, f lirc . the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specified internal clock period can vary with vdd, temperature and process variations. watchdog timer control register a single register, wdtc, controls the required timeout period. wdtc register b i t76543210 name fsyson ws2 ws1 ws0 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por01111010 bit 7 fsyson:f sys control in idle mode 0: disable 1: enable bit 6~4 ws2, ws1, ws0 : wdt time-out period selection 000: 256/f lirc 001: 512/f lirc 010: 1024/f lirc 011: 2048/f lirc 100: 4096/f lirc 101: 8192/f lirc 110: 16384/f lirc 111: 32768/f lirc these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. bit 3~0 undefined bit these bits can be read or written by user software program. watchdog timer operation in these devices the watchdog timer supplied by the f lirc oscillator and is therefore always on. the watchdog timer operates by providing a device reset when its timer overflows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overflows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overflow and reset the device. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 45 september 22, 2011
under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog timer software clear instructions and the third is via a halt instruction. there watchdog timer is cleared using two instructions, clr wdt1 and clr wdt2. these instructions must be executed alternately to successfully clear the watchdog timer. note that if clr wdt1 is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the watchdog timer. similarly after the clr wdt2 instruction has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. for these devices the single clr wdt instruction will have no effect so care must be taken not to use this instruction. the maximum time out period is when the 2 15 division ratio is selected. as an example, with the lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. rev. 1.30 46 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu % ( / ( % 9 2 > #
% f % 2 - 5 > #
: > #
2 ( % - % ! g % ( - ( 2 #
% 2 f 0 #
% watchdog timer
reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 47 september 22, 2011
+ ( ( %
0 ; 8 % + ( (
( % = %
( % = % note: t rstd is power-on delay, typical time=50ms for BS83C24-3, =100ms except BS83C24-3. power-on reset timing chart
res pin although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. the res bit in the ctrl register indicates what kind of reset has occurred. this bit can only be set high by the external reset pin. any other software reset type will clear the bit to zero. if the application reads this bit and it is high then this indicates that a hardware reset has occurred. after reading the bit it should be cleared to zero by the application program. note however that after a power-on reset this pin will be in an unknown condition. rev. 1.30 48 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
0 ; - f - - 0 ' f - 0 0 ' + ( ( + 0 ; 0 - c c + ( ( - 7 4 - 4 c 3 0 0 c note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant external res circuit
%
0 ; 8 % + ( ( 0 ; 4 % + ( (
( % = % note: t rstd is power-on delay, typical time=50ms for BS83C24-3, =100ms except BS83C24-3. res reset timing chart
ctrl register b i t76543210 name resbf hircs1 hircs0 r/w r/w r/w r/w por x 00 x unknown bit 7 resbf : reset pin reset flag -- bs83b08-3/b12-3/b16-3 0: no hardware reset occurred 1: hardware reset occured, this bit is cleared to zero by software. bit 6 unimplemented, read as 0 bits 5,4 hircs1, hircs0 : high frequency clock select described elsewhere bits 3~0 unimplemented, read as 0 low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. one of a range of specified voltage values for v lvr can be selected using configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 and resbf is unchange. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 49 september 22, 2011 # +
%

( % = % note: t rstd is power-on delay, typical time=50ms for BS83C24-3, =100ms except BS83C24-3. low voltage reset timing chart
( % = % ( % %
note: t rstd is power-on delay, typical time=50ms for BS83C24-3, =100ms except BS83C24-3. wdt time-out reset during normal operation timing chart
watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 1~2 clock for lirc. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset u u res or lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are af- fected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack rev. 1.30 50 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu ( % %
wdt time-out reset during sleep or idle timing chart
the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. bs83b08-3 register register reset (power-on) res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (idle or sleep) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 1 1 1 1 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu uuu uuuu tbhp xxx uuu uuu uuu uuu status 00 xxxx uu uuuu 01 uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu integ 00 00 00 00 uu intc0 000 0000 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0 0 0 0 0 0 0 0 u u mfi0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1 1111 1 1111 1 1111 1 1111 u uuuu pac 1 1111 1 1111 1 1111 1 1111 u uuuu papu 0 0000 0 0000 0 0000 0 0000 u uuuu pawu 0 0000 0 0000 0 0000 0 0000 u uuuu wdtc 0111 1010 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 00 00 00 00 uu tmr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmrc 00 000 00 000 00 000 00 000 uu uuu eea 00 0000 00 0000 00 0000 00 0000 uu uuuu eed 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu i2ctoc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu simc0 1110 000 1110 000 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 51 september 22, 2011
register reset (power-on) res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (idle or sleep) sima/simc2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm116dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm116dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctrl x 00 00 1 00 00 1 00 00 u 00 00 u uu uu eec 0000 0000 0000 0000 uuuu note: u stands for unchanged x stands for unknown stands for unimplemented rev. 1.30 52 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
bs83b12-3 register register reset (power-on) res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (idle or sleep) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 1 1 1 1 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu uuu uuuu tbhp xxx uuu uuu uuu uuu status 00 xxxx uu uuuu 01 uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu integ 00 00 00 00 uu intc0 000 0000 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 000 000 000 000 000 000 000 000 uuu uuu mfi0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 00 00 00 00 00 00 00 00 uu uu pa 1 1111 1 1111 1 1111 1 1111 u uuuu pac 1 1111 1 1111 1 1111 1 1111 u uuuu papu 0 0000 0 0000 0 0000 0 0000 u uuuu pawu 0 0000 0 0000 0 0000 0 0000 u uuuu wdtc 0111 1010 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 00 00 00 00 uu tmr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmrc 00 000 00 000 00 000 00 000 uu uuu eea 00 0000 00 0000 00 0000 00 0000 uu uuuu eed 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu i2ctoc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu simc0 1110 000 1110 000 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 53 september 22, 2011
register reset (power-on) res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (idle or sleep) tkm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm116dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm116dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 uuuu pcc 1111 1111 1111 1111 uuuu pcpu 0000 0000 0000 0000 uuuu ctrl x 00 00 1 00 00 1 00 00 u 00 00 u uu uu eec 0000 0000 0000 0000 uuuu tkm216dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm216dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented rev. 1.30 54 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
bs83b16-3/bs83b16g-3 register register reset (power-on) res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (idle or sleep) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 1 1 1 1 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu uuu uuuu tbhp xxx uuu uuu uuu uuu status 00 xxxx uu uuuu 01 uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu integ 00 00 00 00 uu intc0 000 0000 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1 1111 1 1111 1 1111 1 1111 u uuuu pac 1 1111 1 1111 1 1111 1 1111 u uuuu papu 0 0000 0 0000 0 0000 0 0000 u uuuu pawu 0 0000 0 0000 0 0000 0 0000 u uuuu wdtc 0111 1010 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 00 00 00 00 uu tmr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmrc 00 000 00 000 00 000 00 000 uu uuu eea 00 0000 00 0000 00 0000 00 0000 uu uuuu eed 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu i2ctoc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu simc0 1110 000 1110 000 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm016dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 55 september 22, 2011
register reset (power-on) res reset (normal operation) res reset (halt) wdt time-out (normal operation) wdt time-out (idle or sleep) tkm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm0c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm116dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm116dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm1c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ctrl x 00 00 1 00 00 1 00 00 u 00 00 u uu uu eec 0000 0000 0000 0000 uuuu tkm216dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm216dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm2c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm316dh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm316dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tkm3c3 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented rev. 1.30 56 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
BS83C24-3 register register reset (power-on) wdt time-out (normal operation) wdt time-out (halt) * iar0 0000 0000 0000 0000 uuuu uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu iar1 0000 0000 0000 0000 uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu bp 00 00 uu acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp xxxx uuuu uuuu status 00 xxxx 1u uuuu 11 uuuu smod 0000 0011 0000 0011 uuuu uuuu intc3 0000 0000 0000 0000 uuuu uuuu integ 00 00 uu intc0 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 uuuu uuuu mfi1 0000 0000 0000 0000 uuuu uuuu mfi2 0000 0000 0000 0000 uuuu uuuu pa 1 1111 1 1111 u uuuu pac 1 1111 1 1111 u uuuu papu 0 0000 0 0000 u uuuu pawu 0 0000 0 0000 u uuuu wdtc 0111 1010 0111 1010 uuuu uuuu tbc 00 00 uu tmr0 0000 0000 0000 0000 uuuu uuuu tmr0c 00 000 00 000 uu uuu eea 000 0000 000 0000 uuu uuuu eed 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 uuuu uuuu i2ctoc 0000 0000 0000 0000 uuuu uuuu simc0 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 uuuu uuuu bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 57 september 22, 2011
register reset (power-on) wdt time-out (normal operation) wdt time-out (halt) * simd xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 uuuu uuuu tkm016dh 0000 0000 0000 0000 uuuu uuuu tkm016dl 0000 0000 0000 0000 uuuu uuuu tkm0c0 0000 0000 0000 0000 uuuu uuuu tkm0c1 0000 0000 0000 0000 uuuu uuuu tkm0c2 0000 0000 0000 0000 uuuu uuuu tkm0c3 0000 0000 0000 0000 uuuu uuuu tkm116dh 0000 0000 0000 0000 uuuu uuuu tkm116dl 0000 0000 0000 0000 uuuu uuuu tkm1c0 0000 0000 0000 0000 uuuu uuuu tkm1c1 0000 0000 0000 0000 uuuu uuuu tkm1c2 0000 0000 0000 0000 uuuu uuuu tkm1c3 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 uuuu uuuu ctrl x 00 00 u 00 00 u uu uu pd 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 uuuu uuuu tkm216dh 0000 0000 0000 0000 uuuu uuuu tkm216dl 0000 0000 0000 0000 uuuu uuuu tkm2c0 0000 0000 0000 0000 uuuu uuuu tkm2c1 0000 0000 0000 0000 uuuu uuuu tkm2c2 0000 0000 0000 0000 uuuu uuuu tkm2c3 0000 0000 0000 0000 uuuu uuuu tkm316dh 0000 0000 0000 0000 uuuu uuuu tkm316dl 0000 0000 0000 0000 uuuu uuuu tkm3c0 0000 0000 0000 0000 uuuu uuuu tkm3c1 0000 0000 0000 0000 uuuu uuuu tkm3c2 0000 0000 0000 0000 uuuu uuuu tkm3c3 0000 0000 0000 0000 uuuu uuuu tkm416dh 0000 0000 0000 0000 uuuu uuuu tkm416dl 0000 0000 0000 0000 uuuu uuuu rev. 1.30 58 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
register reset (power-on) wdt time-out (normal operation) wdt time-out (halt) * tkm4c0 0000 0000 0000 0000 uuuu uuuu tkm4c1 0000 0000 0000 0000 uuuu uuuu tkm4c2 0000 0000 0000 0000 uuuu uuuu tkm4c3 0000 0000 0000 0000 uuuu uuuu tkm516dh 0000 0000 0000 0000 uuuu uuuu tkm516dl 0000 0000 0000 0000 uuuu uuuu tkm5c0 0000 0000 0000 0000 uuuu uuuu tkm5c1 0000 0000 0000 0000 uuuu uuuu tkm5c2 0000 0000 0000 0000 uuuu uuuu tkm5c3 0000 0000 0000 0000 uuuu uuuu pf 1111 1111 uuuu pfc 1111 1111 uuuu pfpu 0000 0000 uuuu tmr1h 0000 0000 0000 0000 uuuu uuuu tmr1l 0000 0000 0000 0000 uuuu uuuu tmr1c 0000 10 0000 10 uuuu uu eec 0000 0000 uuuu note: * stands for warm reset u stands for unchanged x stands for unknown stands for unimplemented bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 59 september 22, 2011
input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~pf. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list bs83b08-3 register name bit 76543210 pawu d4 d3 d2 d1 d0 papu d4 d3 d2 d1 d0 pa d4 d3 d2 d1 d0 pac d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 bs83b12-3 register name bit 76543210 pawu d4 d3 d2 d1 d0 papu d4 d3 d2 d1 d0 pa d4 d3 d2 d1 d0 pac d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d3 d2 d1 d0 pc d3 d2 d1 d0 pcc d3 d2 d1 d0 rev. 1.30 60 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
bs83b16-3/bs83b16g-3 register name bit 76543210 pawu d4 d3 d2 d1 d0 papu d4 d3 d2 d1 d0 pa d4 d3 d2 d1 d0 pac d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 BS83C24-3 register name bit 76543210 pawu d4 d3 d2 d1 d0 papu d4 d3 d2 d1 d0 pa d4 d3 d2 d1 d0 pac d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d7 d6 d5 d4 d3 d2 d1 d0 pe d7 d6 d5 d4 d3 d2 d1 d0 pec d7 d6 d5 d4 d3 d2 d1 d0 pfpu d3 d2 d1 d0 pf d3 d2 d1 d0 pfc d3 d2 d1 d0 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 61 september 22, 2011
pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using the register papu~pfpu, and are implemented using weak pmos transistors. papu register b i t76543210 name d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w por 00000 bit 7~5 unimplemented, read as 0 bit 4~0 papu : port a bit 4~bit 0 pull-high control 0: disable 1: enable pbpu register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 pbpu port b bit 7~bit 0 pull-high control 0: disable 1: enable pcpu register bs83b12-3 b i t76543210 name d3 d2 d1 d0 r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3~0 pcpu : port c bit 3~bit 0 pull-high control 0: disable 1: enable bs83b16-3/bs83b16g-3/BS83C24-3 b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 pcpu : port c bit 7~bit 0 pull-high control 0: disable 1: enable rev. 1.30 62 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
pdpu, pepu register BS83C24-3 b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 pdpu, pepu : port d~port e bit 7~bit 0 pull-high control 0: disable 1: enable pfpu register BS83C24-3 b i t76543210 name d3 d2 d1 d0 r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3~0 pfpu : port f bit 3~bit 0 pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register b i t76543210 name d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w por 00000 bit 7~5 unimplemented, read as 0 bit 4~0 pawu: port a bit 4~bit 0 wake-up control 0: disable 1: enable bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 63 september 22, 2011
i/o port control register the i/o port has its own control register known as pac~pfc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o port is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register b i t76543210 name d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w por 11111 bit 7~5 unimplemented, read as 0 bit 4~0 i/o port bit 4~bit 0 input/output control 0: output 1: input pbc register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r11111111 bit 7~0 i/o port bit 7 ~ bit 0 input/output control 0: output 1: input rev. 1.30 64 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
pcc register bs83b12-3 b i t76543210 name d3 d2 d1 d0 r/w r/w r/w r/w r/w por 1111 bit 7~4 unimplemented, read as 0 bit 3~0 pcc : port c bit 3~bit 0 input/output control 0: output 1: input bs83b16-3/bs83b16g-3/BS83C24-3 b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r11111111 bit 7~0 pcc : port c bit 7~bit 0 input/output control 0: output 1: input pdc register BS83C24-3 b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r11111111 bit 7~0 pdc : port d bit 7~bit 0 input/output control 0: output 1: input pec register BS83C24-3 b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r11111111 bit 7~0 pec : port e bit 7~bit 0 input/output control 0: output 1: input bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 65 september 22, 2011
pfc register BS83C24-3 b i t76543210 name d3 d2 d1 d0 r/w r/w r/w r/w r/w por 1111 bit 7~4 unimplemented, read as 0 bit 3~0 pfc : port f bit 3~bit 0 input/output control 0: output 1: input i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the first things to consider is port initialisation. after a reset, all of the i/o data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control register, pac~pfc, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register, pa~pf, is first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. rev. 1.30 66 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu + ( ( ! g ' " % % ' "
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timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the devices contain one 8-bit and one 16-bit timers. the 8-bit timer is a general timer. as the 16-bit timer has three different operating modes, it can be configured to operate as a general timer, an external event counter or as a pulse width capture device. the provision of an internal prescaler to the clock circuitry on gives added range to the timers. there are two types of registers related to the timer/event counters. the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and determines how the timer is to be used. the device can have the timer clock configured to come from the internal clock source. in addition, the timer clock source can also be configured to come from an external timer pin. the accompanying table illustrates the timer type list for the devices. device timer type timer register name timer control register name time operating modes bs83b08-3 bs83b12-3 bs83b16-3 bs83b16g-3 8-bit tmr tmrc timer mode BS83C24-3 8-bit tmr0 tmrc0 timer mode 16-bit tmr1l/tmr1h tmrc1 timer mode event counter mode pulse width capture mode timer type summary table bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 67 september 22, 2011
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configuring the timer/event counter input clock source the timer/event counter clock source can originate from various sources, an internal clock or an external pin. the internal clock source is used when the timer is in the timer mode or in the pulse width capture mode. for some timer/event counters, this internal clock source may be first divided by a prescaler, the division ratio of which is conditioned by the timer control register bits. an external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin tc1. depending upon the condition of the t1eg bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer register tmr, tmr0, tmr1l, tmr1h the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. these registers are known as tmr, tmr0, tmr1l and tmr1h. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer/event counter or ffffh for the 16-bit timer/event counters, at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. note that to achieve a maximum full range count of ffh or ffffh, the preload register must first be cleared to all zeros. it should be noted that after power-on, the preload registers will be in an unknown condition. note that if the timer/event counter is in an off condition and data is written to its preload register, this data will be immediately written into the actual counter. however, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. timer control register tmrc, tmr0c, tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. the timer control register is known as tmrc, tmr0c and tmr1c. the tmrc or tmr0c is used to control the 8-bit timer while the tmr1c are used for 16-bit timer. it is the timer control register together with its corresponding timer register that control the full operation of the timer/event counter. before the timer can be used, it is essential that the timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. the timer-on bit, which is bit 4 of the timer control register and known as ton, t0on or t1on bit, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. bits 0~2 of the tmrc or tmr0c registers determine the division ratio of the input clock prescaler. in addition, the ts, t0s and t1s bits select the internal clock source. rev. 1.30 68 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu , - * . '
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16-bit timer/event counter 1
the 16-bit timer, tmr1, can operate in three different modes. to choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width capture mode, bits 7 and 6 of the timer control register, which are known as the bit pair t1m1/t1m0, must be set to the required logic levels. if the tmr1 is in the event count or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as t1eg. tmr0c register bs83b08-3/b12-3/b16-3/b16g-3 bit76543210 name ts ton tpsc2 tpsc1 tpsc0 r/w r/w r/w r/w r/w r/w por 00 000 bits 7, 6 unimplemented, read as 0 bit 5 ts : timer/event counter clock source 0: f sys 1: f lirc bit 4 ton : timer/event counter counting enable 0: disable 1: enable bit 3 unimplemented, read as 0 bits 2~0 tpsc2~tpsc0 : timer prescaler rate selection timer internal clock= 000: f tp 001: f tp /2 010: f tp /4 011: f tp /8 100: f tp /16 101: f tp /32 110: f tp /64 111: f tp /128 BS83C24-3 bit76543210 name t0s t0on t0psc2 t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w por 00 000 bits 7, 6 unimplemented, read as 0 bit 5 t0s : timer/event counter clock source 0: f sys 1: f lirc bit 4 t0on : timer/event counter counting enable 0: disable 1: enable bit 3 unimplemented, read as 0 bits 2~0 t0psc2~t0psc0 : timer prescaler rate selection timer internal clock= 000: f tp 001: f tp /2 010: f tp /4 011: f tp /8 100: f tp /16 101: f tp /32 110: f tp /64 111: f tp /128 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 69 september 22, 2011
tmr1c register BS83C24-3 bit76543210 name t1m1 t1m0 t1s t1on t1eg pfdc r/w r/w r/w r/w r/w r/w r/w por000010 bits 7, 6 t1m1, t1m0: timer 1 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode bit 5 t1s : timer clock source 0: f sys /4 1: lirc oscillator bit 4 t1on : timer/event counter counting enable 0: disable 1: enable bit 3 t1eg: event counter active edge selection 0: count on rising edge 1: count on falling edge pulse width capture active edge selection 0: start counting on falling edge, stop on rising edge 1: start counting on raising edge, stop on falling edge bit 2 pfdc: i/o or pfd selection bit 0: i/o 1: pfd bits 1, 0 unimplemented, read as 0 8-bit timer/event counter operating mode the timer/event counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the timer/event counter overflows. the internal clock is used as the timer clock. the timer input clock source is either the f sys /4 or the lirc oscillator. however, this timer clock source is further divided by a prescaler, the value of which is determined by the bits tpsc2~tpsc0 or t0psc2~t0psc0 in the timer control register. the timer-on bit, ton or t0on, must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the et0i bits of the intc1 register are reset to zero. 16-bit timer/event counter 1 operating modes -- BS83C24-3 the 16-bit timer has three different operating modes, it can be configured to operate as a general timer, an external event counter or as a pulse width capture device via the t1m1 and t1m0 bits in the tmr1c register. timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the timer/event counter overflows. to operate in this mode, the operating mode select bit pair, t1m1/t1m0, in the timer control register must be set to the correct value as shown. rev. 1.30 70 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock is used as the timer clock. the timer input clock source is either the f sys /4 or the lirc oscillator. the timer-on bit, t1on must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the et1i bits of the intc3 register are reset to zero. event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tc1 pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 in this mode, the external timer tc1 pin is used as the timer/event counter clock source. after the other bits in the timer control register have been setup, the enable bit t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, t1eg, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the t1eg is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register is reset to zero. as the external timer pin is shared with an i/o pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the idle/sleep mode, the timer/event counter will continue to record externally changing logic events on the timer input tc1 pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 71 september 22, 2011 4 0 5 " 0 % " " " ! " 4 6 4 event counter mode timing chart (t1eg=1) " " " * ! & ! 4 4 4 . 4 . 4 time mode timing chart
pulse width capture mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair, t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the pulse width capture mode bit7 bit6 11 in this mode the internal clock, f sys /4 or the lirc, is used as the internal clock for the 16-bit timer/event counter. after the other bits in the timer control register have been setup, the enable bit t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit t1eg, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the tc1 pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. the timer cannot begin further pulse width capture until the enable bit is set high again by the program. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register is reset to zero. as the tc1 pin is shared with an i/o pin, to ensure that the pin is configured to operate as a pulse width capture pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width capture mode, the second is to ensure that the port control register configures the pin as an input. rev. 1.30 72 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu 4 4 4 6 4 - 0 5 " " " & ! * . # + 7 0 1 8 * ! & ! " " ! " * ! & ! & ' % 9 " ' : pulse width capture mode timing chart (t1eg=0)
prescaler bits t0psc0~t0psc2 of the tmr0c or tpsc0~tpsc2 of the tmrc register can be used to define a division ratio for the internal clock source of the 8-bit timer/event counter enabling longer time out periods to be setup. pfd function the programmable frequency divider provides a means of producing a variable frequency output suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency generator. as the pins are shared with i/o pins, the function is selected using the tmr1c register. the timer/event counter 1 overflow signal is the clock source for the pfd function. the output frequency is controlled by loading the required values into the timer registers to give the required division ratio. the counter will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the pfd outputs to change state. the counter will then be automatically reloaded with the preload register value and continue counting-up. if the tmr1c register has selected the pfd function, it is essential for the port e control register pec, to setup the pfd pin as output. the bit pe0 must be set high to activate the pfd. the output data bit can be used as the on/off control bit for the pfd outputs. note that the pfd output will all be low if the output data bit is cleared to zero. using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width capture mode, requires the use of an external timer pin for its operation. as this pin is a shared pin it must be configured correctly to ensure that it is setup for use as a timer/event counter input pin. this is achieved by ensuring that the mode select bits in the timer/event counter control register select either the event counter or pulse width capture mode. additionally the corresponding port control register bit must be set high to ensure that the pin is setup as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. for the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 73 september 22, 2011 * % + / ) ; 0 ) / ) * ! & ! 0 pfd function
the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialized before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control register. when the timer/event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. if the timer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the halt instruction to enter the idle/sleep mode. timer program example-timer/event counter 0 the program shows how the timer/event counter 0 registers are setup along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counters to be in the timer mode, which uses the internal system clock as their clock source. pfd programming example org 04h ; external interrupt vector org 08h ; timer counter 0 interrupt vector jmp tmr0int ; jump here when timer 0 overflows : : org 20h ; main program : : ;internal timer 0 interrupt routine tmr0int: : ; timer 0 main program placed here : : begin: ;setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr,a mov a,001h ; setup timer 0 control register mov tmrc,a ; timer mode and prescaler set to /2 ;setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a : : set tmrc.4 ; start timer 0 rev. 1.30 74 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
touch key function each device provides multiple touch key functions. the touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. touch key structure the touch keys are pin shared with the pb, pc and pd logic i/o pins, with the desired function chosen via register bits. keys are organised into groups of four, with each group known as a module and having a module number, m0 to m5.each module contains its own control logic circuits and register set. examination of the register names will reveal the module number it is referring to. device keys - n touch key module touch key shared i/o pin bs83b08-3 8 m0 k1~k4 pb0~pb3 m1 k5~k8 pb4~pb7 bs83b12-3 12 m0 k1~k4 pb0~pb3 m1 k5~k8 pb4~pb7 m2 k9~k12 pc0~pc3 bs83b16-3 bs83b16g-3 16 m0 k1~k4 pb0~pb3 m1 k5~k8 pb4~pb7 m2 k9~k12 pc0~pc3 m3 k13~k16 pc4~pc7 BS83C24-3 16 m0 k1~k4 pb0~pb3 m1 k5~k8 pb4~pb7 m2 k9~k12 pc0~pc3 m3 k13~k16 pc4~pc7 m4 k17~k20 pd0~pd3 m5 k21~k24 pd4~pd7 general purpose data memory bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 75 september 22, 2011
touch key register definition each touch key module, which contains four touch key functions, has its own suite of six registers. the following table shows the register set for each touch key module. the mn within the register name refers to the touch key module number and has a range of m0 to m5. name usage tkmn16dh 16-bit c/f counter high byte tkmn16dl 16-bit c/f counter low byte tkmnc0 control register 0 key select/x2 freq/filter control/frequency select tkmnc1 control register 1 sensor oscillator control/touch key or i/o select. tkmnc2 control register 2 counter on-off and clear control/reference clock control/start bit tkmnc3 control register 3 counter overflow bits/reference oscillator overflow time select register listing register name bit 76543 2 1 0 tkmn16dh d7 d6 d5 d4 d3 d2 d1 d0 tkmn16dl d7 d6 d5 d4 d3 d2 d1 d0 tkmnc0 mnmxs1 mnmxs0 d5 d4 d3 d2 d1 d0 tkmnc1 mnk4oen mnk3oen mnk2oen mnk1oen mnk4io mnk3io mnk2io mnk1io tkmnc2 mn16cton d6 mnst mnroen mnrcclr mn16ctclr d1 mnros tkmnc3 d9 d8 mnrcov mn16ctov d3 mnrovs2 mnrovs1 mnrovs0 touch key module tkmn16dh register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 module n 16-bit counter high byte contents tkmn16dl register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr p o r00000000 bit 7~0 module n 16-bit counter low byte contents rev. 1.30 76 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
tkmnc0 register b i t76543210 name mnmxs1 mnmxs0 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bits 7~6 mnmxs1, mnmxs0 : multiplexer key select bit module number mnmxs1 mnmxs0 m0 m1 m2 m3 m4 m5 0 0 key 1 key 5 key 9 key 13 key 17 key 21 0 1 key 2 key 6 key 10 key 14 key 18 key 22 1 0 key 3 key 7 key 11 key 15 key 19 key 23 1 1 key 4 key 8 key 12 key 16 key 20 key 24 bit 5~0 d5~d0 : these bits must be set to the binary value 011000 tkmnc1 register b i t76543210 name mnk4oen mnk3oen mnk2oen mnk1oen mnk4io mnk3io mnk2io mnk1io r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bits 7~4 mnk4oen~ mnk1oen: key selector control mnk4oen m0 m1 m2 m3 m4 m5 key 4 key 8 key 12 key 16 key 20 key 24 0 disable 1 enable mnk3oen m0 m1 m2 m3 m4 m5 key 3 key 7 key 11 key 15 key 19 key 23 0 disable 1 enable mnk2oen m0 m1 m2 m3 m4 m5 key 2 key 6 key 10 key 14 key 18 key 22 0 disable 1 enable mnk1oen m0 m1 m2 m3 m4 m5 key 1 key 5 key 9 key 13 key 17 key 21 0 disable 1 enable bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 77 september 22, 2011
bits 3~0 i/o pin or touch key function select mnk4io m0 m1 m2 m3 m4 m5 pb3/key 4 pb7/key 8 pc3/key 12 pc7/key 16 pd3/key 20 pd7/key 24 0 i/o pin 1 touch key mnk3io m0 m1 m2 m3 m4 m5 pb2/key 3 pb6/key 7 pc2/key 11 pc6/key 15 pd2/key 19 pd6/key 23 0 i/o pin 1 touch key mnk2io m0 m1 m2 m3 m4 m5 pb1/key 2 pb5/key 6 pc1/key 10 pc5/key 14 pd1/key 18 pd5/key 22 0 i/o pin 1 touch key mnk1io m0 m1 m2 m3 m4 m5 pb0/key 1 pb4/key 5 pc0/key 9 pc4/key 13 pd0/key 17 pd4/key 21 0 i/o pin 1 touch key tkmnc2 register bit7654 3 210 name mn16cton mnst mnroen mnrcclr mn16ctclr mnros r/w r/w r/w r/w r/w r/w r/w por 0 0000 0 bit 7 mn16cton : 16-bit c/f counter control 0: disable 1: enable bit 6 reserved bit, must not be modified. bit 5 mnst : time slot counter start control 0: time slot counter stopped 0 1: enable time slot counter. when this bit changes from low to high the time slot counter will be enabled and the touch sense procedure started. when the time slot counter has completed its counting an interrupt will be generated. bit 4 mnroen : reference clock control 0: disable 1: enable bit 3 mnrcclr : time slot counter clear control 0: no change 1: clear counter this bit must be first set to 1 and then to 0. bit 2 mn16ctclr : 16-bit c/f counter clear control 0: no change 1: clear counter this bit must be first set to 1 and then to 0. bit 1 reserved bit, must not be modified. bit 0 mnros : time slot counter clock source 0: reference clock 1: sense key oscillator m0: key 4, m1: key 8, m2: key12, m3: key 16, m4: key 20, m5: key 24 rev. 1.30 78 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
tkmnc3 register b i t76543210 name d7 d6 mnrcov mn16ctov mnrovs2 mnrovs1 mnrovs0 r/w r r r r/w r/w r/w r/w por0000 00 0 bit 7~6 d7, d6 : read only bits -- unknown values bit 5 mnrcov : time slot counter overflow flag 0: no overflow 1: overflow bit 4 mn16ctov : 16-bit c/f counter overflow flag 0: no overflow 1: overflow bit 3 reserved bit, must not be modified. bits 2~1 mnrovs2~mnrovs0 : time slot counter overflow time setup 000: 64 count 001: 128 count 010: 256 count 011: 512 count 100: 1024 count 101: 2048 count 110: 4096 count 111: 8192 count touch key operation when a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. by using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. using an internal programmable divider the reference clock is used to generate a fixed time period. by counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. the device contains four touch key inputs which are shared with logical i/o pins, with the desired function selected using register bits. the touch key module also has its own interrupt vectors and set of interrupts flags. during this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. at the end of the fixed reference clock time interval, a touch key interrupt signal will be generated. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 79 september 22, 2011
touch key interrupt each touch key module, which consists of four touch keys, has two independent interrupts, one for each of the, 16-bit c/f counter and time slot counter. the time slot counter interrupt has its own interrupt vector while the 16-bit c/f counter interrupts are contained within the multi-function interrupts and therefore do not have their own vector. care must be taken during programming as the 16-bit c/f counter interrupt flags contained within the multi-function interrupts will not be automatically reset upon entry into the interrupt service routine but rather must be reset manually by the application program. more details regarding the touch key interrupts are located in the interrupt section of the datasheet. programming considerations after the relevant registers are setup, the touch key detection process is initiated the changing the mnst bit from low to high. this will enable and synchronise all relevant oscillators. the mnrcov flag, which is the time slot counter flag will go high and remain high until the counter overflows. when this happens an interrupt signal will be generated. when the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. rev. 1.30 80 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu c/f & mux. mux. reference clock touch key (1 set = touch key*4) key0 key1 key2 key3 16-bit c/f counter 16-bit c/f counter overflow flag 16-bit c/f counter int flag time slot counter time slot counter overflow flag time slot counter int flag enable time slot counter clock select touch switch module block diagram ! 7 ! , * ! " < - * = " < 6 * = " < * = " < * = 0 5 " " , * ! 7 < 9 ! 7 ! , * ! 0 5 " " , * ! 7 < 9 ! 7 ! , * ! 0 5 " " , * ! 7 < 9 ! 7 ! , * ! 0 5 " " , * ! 7 < 9 touch key or i/o function select
serial interface module sim these devices contain a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim pins are pin shared with other i/o pins and must be selected using the simen bit in the simc0 register. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spi interface specification can control multiple slave devices from a single master, but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must first be enabled by setting the correct bits in the simc0 and simc2 registers. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be as i/o function. the spi function in this device offers the following features: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 81 september 22, 2011

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spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 76543210 simc0 sim2 sim1 sim0 simen simd d7 d6 d5 d4 d3 d2 d1 d0 simc2 d7 d6 ckpolb ckeg mls csen wcol trf spi registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the de- vice can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown rev. 1.30 82 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu ) $ ! ) " ) * " ) 5 ,
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there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision flag etc. simc0 register b i t76543210 name sim2 sim1 sim0 simen r/w r/w r/w r/w r/w por 1 1 1 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f lirc 100: unused 101: spi slave mode 110: i 2 c slave mode 111: unused these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4~2 unimplemented, read as 0 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared, the sdi, sdo, sck and scs , or sda and scl lines will be as i/o function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is configured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be first initialised by the application program. if the sim is configured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 83 september 22, 2011
simc2 register b i t76543210 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~6 undefined bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and as i/o function. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision flag 0: no collision 1: collision the wcol flag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 trf : spi transmit/receive complete flag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete flag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt. rev. 1.30 84 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the configurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various configurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 85 september 22, 2011 < ? < * $ 8 @ < ? < * $ 8 @ ) * ) ) & ! ) , ) ) a , ) ) b , ) ) - , ) 6 ) 6 , ) - ) , ) b ) , ) a ) , ) > ) ? ) * ' " 7 " ! " < ' @ spi slave mode timing ckeg=0 < ? < * $ 8 2 < 0 1 8 @ 0 . 2 0 . 8 0 . 8 2 0 . 8 ? 0 5 " ! # c 7 @ < ? < * $ 8 2 < 0 1 8 @ < ? < * $ 8 2 < 0 1 8 @ < ? < * $ 8 2 < 0 1 8 @ ) * ? < 0 1 8 @ ) * ? < 0 1 8 @ ) ) & ! ) , ) ) a , ) ) b , ) ) - , ) 6 ) 6 , ) - ) , ) b ) , ) a ) , ) ) , ) ) a , ) ) b , ) ) - , ) 6 ) 6 , ) - ) , ) b ) , ) a ) , ) > ) spi master mode timing
rev. 1.30 86 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu 0 . 8 > ) " ) > * 8 d > * " " & ' d ?
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i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 87 september 22, 2011 ) % % ) % ) % % 3 ) ) ) e i 2 c master slave bus connection )
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the debounce time of the i 2 c interface uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, is 2 system clocks. to achieve the required i 2 c data transfer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) 2 system clock debounce f sys > 4mhz f sys > 10mhz i 2 c minimum f sys frequency i 2 c registers there are four control registers associated with the i 2 c bus, simc0, simc1, sima and i2ctoc and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. the sim pins are pin shared with other i/o pins and must be selected using the simen bit in the simc0 register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 76543210 simc0 sim2 sim1 sim0 simen simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d6 d5 d4 d3 d2 d1 d0 sima iica6 iica5 iica4 iica3 iica2 iica1 iica0 d0 i2ctoc i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 i 2 c register list rev. 1.30 88 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu e
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simc0 register b i t76543210 name sim2 sim1 sim0 simen r/w r/w r/w r/w r/w por 1 1 1 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f lirc 100: unused 101: spi slave mode 110: i 2 c slave mode 111: unused these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4~2 unimplemented, read as 0 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared, the sdi, sdo, sck and scs , or sda and scl lines will be as i/o function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. if the sim is configured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be first initialised by the application program. if the sim is configured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 89 september 22, 2011
simc1 register b i t76543210 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r p o r10000001 bit 7 hcf:i 2 c bus data transfer completion flag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas:i 2 c bus address match flag 0: not address match 1: address match the hass flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the flag will be low. bit 5 hbb:i 2 c bus busy flag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak:i 2 c bus transmit acknowledge flag 0: slave send acknowledge flag 1: slave do not send acknowledge flag the txak bit is the transmit acknowledge flag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw :i 2 c slave read/write flag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas flag is set high, the slave device will check the srw flag to determine whether it should be in transmit mode or receive mode. if the srw flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu:i 2 c address match wake-up control 0: disable 1: enable this bit should be set to 1 to enable i 2 c address match wake-up from sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. bit 0 rxak:i 2 c bus receive acknowledge flag 0: slave receive acknowledge flag 1: slave do not receive acknowledge flag the rxak flag is the receiver acknowledge flag. when the rxak flag is 0 , it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak flag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak flag is 1 . when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. rev. 1.30 90 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
i2ctoc register b i t76543210 name i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7 i2ctoen :i 2 c time-out control 0: disable 1: enable bit 6 i2ctof : time-out flag 0: no time-out 1: time-out occurred bit 5~0 i2ctos5 ~ i2ctos0 : time-out time definition i 2 c time-out clock source is f lirc /32. i 2 c time-out time is given by: [i2ctos5 : i2ctos0]+1) x (32/f lirc ) the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the de - vice can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. simd register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown sima register b i t76543210 name iica6 iica5 iica4 iica3 iica2 iica1 iica0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown bit 7~1 iica6~ iica0 :i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6~bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register define the device slave address. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefined bit this bit can be read or written by user software program. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 91 september 22, 2011
i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must first check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. step 2 write the slave address of the device to the i 2 c bus address register sima. step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt. i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. rev. 1.30 92 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu > % e ' ' e 0 8 0 0 . $ ! " ! & 8 d . 0 > " ! & 1 " 0 / ' ' + 7 " $ !
1 " i 2 c bus initialisation flow chart
slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status flag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defines whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw flag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw flag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 93 september 22, 2011 ) 8 ? = @ e 8 % e ' ' ? = @
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i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas flag is high, the addresses have matched and the slave device must check the srw flag to determine if it is to be a transmitter or a receiver. if the srw flag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1 . if the srw flag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0 . i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0 , before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must first write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. rev. 1.30 94 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu c e e 8 d c 8 d
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i 2 c time-out control in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, clock, a time-out function is provided. if the clock source to the i 2 c is not received then after a fixed time period, the i 2 c circuitry and registers will be reset. the time-out counter starts counting on an i 2 c bus start & address match condition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the time-out setup by the i2ctoc register, then a time-out condition will occur. the time-out function will stop when an i 2 c stop condition occurs. when an i 2 c time-out counter overflow occurs, the counter will stop and the i2ctoen bit will be cleared to zero and the i2ctf bit will be set high to indicate that a time-out condition as occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrrupt vector. when an i 2 c time-out occurs the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out simdr, simar, simc0 no change simc1 reset to por condition i 2 c registers after time-out the i2ctof flag can be cleared by the application program. there are 64 time-out periods which can be selected using bits in the i2ctoc register. the time-out time is given by the formula: ((1~64) 32)/f lirc . this gives a range of about 1ms to 64ms. note also that the lirc oscillator is continuously enabled. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 95 september 22, 2011 # ! ! " # ! ! " " " % " " ) e
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interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a touch action or timer/event counter overflow requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int pin, while the internal interrupts are generated by various internal functions such as the touch keys, timer/event counter, time base, sim etc. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the first is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specific pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request flag. function enable bit request flag notes global emi int pin inte intf touch key module tkmne tkmnf n=0~5 sim sime simf eeprom dee def multi-function mfne mfnf n=0~2 time base tbe tbf timer/event counter tne, te tnf, tf n=0~1 touch key module 16-bit counter mn16cte mn16ctf n=0~5 interrupt register bit naming conventions rev. 1.30 96 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
interrupt register contents bs83b08-3 name bit 76543210 integ ints1 ints0 intc0 tkm1f tkm0f intf tkm1e tkm0e inte emi intc1 tf mf0f def simf te mf0e dee sime intc2 tbf tbe mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 bs83b12-3 name bit 76543210 integ ints1 ints0 intc0 tkm1f tkm0f intf tkm1e tkm0e inte emi intc1 tf mf0f def simf te mf0e dee sime intc2 tkm2f mf1f tbf tkm2e mf1e tbe mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 mfi1 m216ctf d4 m216cte d0 bs83b16-3/bs83b16g-3 name bit 76543210 integ ints1 ints0 intc0 tkm1f tkm0f intf tkm1e tkm0e inte emi intc1 tf mf0f def simf te mf0e dee sime intc2 tkm3f tkm2f mf1f tbf tkm3e tkm2e mf1e tbe mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 mfi1 m316ctf d6 m216ctf d4 m316cte d2 m216cte d0 BS83C24-3 name bit 76543210 integ ints1 ints0 intc0 tkm1f tkm0f intf tkm1e tkm0e inte emi intc1 t0f mf0f def simf t0e mf0e dee sime intc2 tkm3f tkm2f mf1f tbf tkm3e tkm2e mf1e tbe intc3 tkm5f tkm4f mf2f t1f tkm5e tkm4e mf2e t1e mfi0 m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 mfi1 m316ctf d6 m216ctf d4 m316cte d2 m216cte d0 mfi2 m516ctf d6 m416ctf d4 m516cte d2 m416cte d0 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 97 september 22, 2011
integ register -- all devices b i t76543210 name ints1 ints0 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 ints1, ints0 : interrupt edge control for int pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register -- all devices b i t76543210 name tkm1f tkm0f intf tkm1e tkm0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 tkm1f : touch key module 1 interrupt request flag 0: no request 1: interrupt request bit 5 tkm0f : touch key module 0 interrupt request flag 0: no request 1: interrupt request bit 4 intf : int pin interrupt request flag 0: no request 1: interrupt request bit 3 tkm1e : touch key module 1 interrupt control 0: disable 1: enable bit 2 tkm0e : touch key module 0 interrupt control 0: disable 1: enable bit 1 inte : int pin interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable rev. 1.30 98 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
intc1 register -- bs83b08-3/b12-3/b16-3/b16g-3 b i t76543210 name tf mf0f def simf te mf0e dee sime r/w r/w r/w r/w r/w r/w r/w por 0 0 0 000 bit 7 tf : timer/event counter interrupt request flag 0: no request 1: interrupt request bit 6 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 simf : sim interrupt reqeust flag 0: no request 1: interrupt request bit 3 te : timer/event counter interrupt control 0: disable 1: enable bit 2 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 99 september 22, 2011
intc1 register -- BS83C24-3 b i t76543210 name t0f mf0f def simf t0e mf0e dee sime r/w r/w r/w r/w r/w r/w r/w por 0 0 0 000 bit 7 t0f : timer/event counter interrupt 0 request flag 0: no request 1: interrupt request bit 6 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 simf : sim interrupt reqeust flag 0: no request 1: interrupt request bit 3 t0e : timer/event counter 0 interrupt control 0: disable 1: enable bit 2 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable intc2 register -- bs83b08-3 b i t76543210 name tbf tbe r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as 0 bit 4 tbf : time base interrupt request flag 0: no request 1: interrupt request bit 3~1 unimplemented, read as 0 bit 0 tbe : time base interrupt control 0: disable 1: enable rev. 1.30 100 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
intc2 register -- bs83b12-3 b i t76543210 name tkm2f mf1f tbf tkm2e mf1e tbe r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 tkm2f : touch key module 2 interrupt request flag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 tbf : time base interrupt request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 tkm2e : touch key module 2 interrupt control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 tbe : time base interrupt control 0: disable 1: enable intc2 register -- bs83b16-3/bs83b16g-3/BS83C24-3 b i t76543210 name tkm3f tkm2f mf1f tbf tkm3e tkm2e mf1e tbe r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 tkm3f : touch key module 3 interrupt request flag 0: no request 1: interrupt request bit 6 tkm2f : touch key module 2 interrupt request flag 0: no request 1: interrupt request bit 5 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 tbf : time base interrupt request flag 0: no request 1: interrupt request bit 3 tkm3e : touch key module 3 interrupt control 0: disable 1: enable bit 2 tkm2e : touch key module 2 interrupt control 0: disable 1: enable bit 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 0 tbe : time base interrupt control 0: disable 1: enable bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 101 september 22, 2011
intc3 register -- BS83C24-3 b i t76543210 name tkm5f tkm4f mf2f t1f tkm5e tkm4e mf2e t1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 tkm5f : touch key module 5 interrupt request flag 0: no request 1: interrupt request bit 6 tkm4f : touch key module 4 interrupt request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 t1f : timer/event counter 1 interrupt request flag 0: no request 1: interrupt request bit 3 tkm5e : touch key module 5 interrupt control 0: disable 1: enable bit 2 tkm4e : touch key module 4 interrupt control 0: disable 1: enable bit 1 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 0 t1e : timer/event counter 1 interrupt control 0: disable 1: enable mfi0 register -- all devices bit76543210 name m116ctf d6 m016ctf d4 m116cte d2 m016cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 m116ctf : touch key module 1 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 6 d6 : reserved bit, must not be modified. bit 5 m016ctf : touch key module 0 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 4 d4 : reserved bit, must not be modified. bit 3 m116cte : touch key module 1 16-bit timer interrupt control 0: disable 1: enable bit 2 d2 : reserved bit, must not be modified. bit 1 m016cte : touch key module 0 16-bit timer interrupt control 0: disable 1: enable bit 0 d0 : reserved bit, must not be modified. rev. 1.30 102 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
mfi1 register -- bs83b12-3 bit76543210 name m216ctf d4 m216cte d0 r/w r/w r/w r/w r/w por 00 00 bit 7~6 unimplemented, read as 0 bit 5 m216ctf : touch key module 2 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 4 d4 : reserved bit, must not be modified. 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 m216cte : touch key module 2 16-bit timer interrupt control 0: disable 1: enable bit 0 d0 : reserved bit, must not be modified. 0: disable 1: enable mfi1 register -- bs83b16-3/bs83b16g-3/BS83C24-3 bit76543210 name m316ctf d6 m216ctf d4 m316cte d2 m216cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 m316ctf : touch key module 3 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 6 d6 : reserved bit, must not be modified. bit 5 m216ctf : touch key module 2 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 4 d4 : reserved bit, must not be modified. bit 3 m316cte : touch key module 3 16-bit timer interrupt control 0: disable 1: enable bit 2 d2 : reserved bit, must not be modified. bit 1 m216cte : touch key module 2 16-bit timer interrupt control 0: disable 1: enable bit 0 d0 : reserved bit, must not be modified. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 103 september 22, 2011
mfi2 register -- BS83C24-3 bit76543210 name m516ctf d6 m416ctf d4 m516cte d2 m416cte d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 m516ctf : touch key module 5 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 6 d6 : reserved bit, must not be modified. bit 5 m416ctf : touch key module 4 16-bit counter interrupt request flag 0: no request 1: interrupt request bit 4 d4 : reserved bit, must not be modified. bit 3 m516cte : touch key module 5 16-bit timer interrupt control 0: disable 1: enable bit 2 d2 : reserved bit, must not be modified. bit 1 m416cte : touch key module 4 16-bit timer interrupt control 0: disable 1: enable bit 0 d0 : reserved bit, must not be modified. interrupt operation when the conditions for an interrupt event occur, such as a touch key counter overflow, timer/event counter overflow, etc. the relevant interrupt request flag will be set. whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp instruction which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is rev. 1.30 104 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
applied. all of the interrupt request flags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device enters the sleep or idle mode. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 105 september 22, 2011 / - c ( c - c ( c c c 3 + 0 ! ' = ' "
0 0 5 " . 0 < / < 0 $ / $ $ 0 0 0 c c < / ! 7 < 9 ' ! < 0 / 0 ) 0 / 0 0
* ) 0 0 / / / 0 0 5 5 /

5 5 / 0 " = $ 5 5 0
g ! / # # " ! "

g ! / # # ! "
0 " ! & .
g ! / 0 " = $ 0 " = 9 c 7 . / ! 7 < 9 ' ! : / ! " " , 0 % " ! " 0 0 c < 6 / ! 7 < 9 ' ! 6 < 6 0 0 6 a 0 6 a # = % + 6 a / a 0 a # = % + a / - c ( c / / < / ! 7 < 9 ' ! : / ! " " / 0 0 < 0 0 0 0 a 0 a 0 " ! & .
g ! / 0 " = $ a # = % + a / a # = % + a / interrupt structure -- bs83b08-3/b12-3/b16-3/b16g-3
rev. 1.30 106 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu / - c ( c - c ( c c c 3 + 0 ! ' = ' "
0 0 5 " . 0 < / < 0 $ / $ $ 0 0 0 c c < / ! 7 < 9 ' ! < 0 / 0 ) 0 / 0 0
* ) 0 0 / / / 0 0 5 5 /

5 5 / 0 " = $ 5 5 0
g ! / # # " ! "

g ! / # # ! "
0 " ! & .
g ! / 0 " = $ 0 " = 9 c 7 . / ! 7 < 9 ' ! : / ! " " , 0 % " ! " 0 0 c < 6 / ! 7 < 9 ' ! 6 < 6 0 0 6 a 0 6 a # = % + 6 a / a 0 a # = % + a / - c ( c / / < / ! 7 < 9 ' ! : / ! " " / 0 0 < 0 0 0 0 a 0 a 0 " ! & .
g ! / 0 " = $ a # = % + a / a # = % + a / 6 c / 0 0 6 c < b / ! 7 < 9 ' ! b < b 0 0 b a 0 b a # = % + b a / - a 0 - a # = % + - a / 6 - c 6 ( c / / < - / ! 7 < 9 ' ! - : / ! " " / 0 0 < - 0 0 , 0 % " ! " interrupt structure -- BS83C24-3
external interrupt the external interrupt is controlled by signal transitions on the int pin. an external interrupt request will take place when the external interrupt request flag, intf, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, inte, must first be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request flag, intf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within these devices there are one or two multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from the touch key module timer interrupt sources. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts, namely the touch key module timer interrupts, will not be automatically reset and must be manually reset by the application program. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 107 september 22, 2011
time base interrupts the function of the time base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its respective timer function. when this happens its respective interrupt request flag, tbf, will be set. to allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bit, tbe, must first be set. when the interrupt is enabled, the stack is not full and the time base overflows, a subroutine call to its respective vector location will take place. when the interrupt is serviced, the respective interrupt request flag, tbf, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal with a fixed time period. its clock source originates from the internal clock source f sys or f lirc . this clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. tbc register bit76543210 name tb1 tb0 r/w r/w r/w por 00 bit 7~6 unimplemented, read as 0 bit 5~4 tb1~tb0 : select time base time-out period 00: 1024/f tp 01: 2048/f tp 10: 4096/f tp 11: 8192/f tp bit 3~0 unimplemented, read as 0 rev. 1.30 108 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu ) % ' = 9 h 6 $ h $ $ " ! &
time base structure
timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, te, t0e or t1e, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request flag, tf, t0f or t1f, is set, a situation that will occur when the relevant timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer interrupt request flag, tf, t0f or t1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def, is set, which occurs when an eeprom write cycle end. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle end, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automatically cleared. as the def flag will not be automatically cleared, it has to be cleared by the application program. touch key interrupts for a touch key interrupt to occur, the global interrupt enable bit, emi, and the corresponding touch key interrupt enable tkmne must be first set. an actual touch key interrupt will take place when the touch key request flag. tkmnf, is set, a situation that will occur when the 13-bit time slot counter in the relevant touch key module overflows. when the interrupt is enabled, the stack is not full and the touch key time slot counter overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the touch key interrupt request flag, tkmnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. sim interrupt a sim interrupt request will take place when the sim interrupt request flag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must first be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective interrupt vector, will take place. when the serial interface interrupt is serviced, the sim interrupt request flag, sif, will be automatically cleared and the emi bit will be automatically cleared to disable other interrupts. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 109 september 22, 2011
interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request flag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. rev. 1.30 110 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
application circuits note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is significant. # may be resistor or capacitor. the resistance of # must be greater than 1k or the capacitance of * must be less than 1nf. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 111 september 22, 2011 < 0 < 0 , *
0 3 ) ) 3 : / 3 ) )

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instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be implemented within 1 s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. rev. 1.30 112 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 113 september 22, 2011
instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none rev. 1.30 114 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
mnemonic description cycles flag affected bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 115 september 22, 2011
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc + [m] + c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z rev. 1.30 116 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cy - cle instruction. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con- junction with clr wdt2 and must be executed alternately with clr wdt2 to have ef- fect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in con - junction with clr wdt1 and must be executed alternately with clr wdt1 to have ef - fect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 117 september 22, 2011
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain un - changed. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the con - tents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf rev. 1.30 118 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 119 september 22, 2011
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pend- ing when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data mem - ory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none rev. 1.30 120 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 re - places the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 121 september 22, 2011
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec- ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none rev. 1.30 122 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the spec - ified data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruc- tion. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the re- sult is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the re - sult is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is neg - ative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 123 september 22, 2011
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain un - changed. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following in - struction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none rev. 1.30 124 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 125 september 22, 2011
package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.386 0.402 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010
0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 9.80 10.21 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25
0 8 rev. 1.30 126 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu

16-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.189 0.197 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010
0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 4.80 5.00 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25
0 8 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 127 september 22, 2011

20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.496 0.512 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013
0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 12.60 13.00 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33
0 8 rev. 1.30 128 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu

20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.158 c 0.008 0.012 c 0.335 0.347 d 0.049 0.065 e 0.025 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010
0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 4.01 c 0.20 0.30 c 8.51 8.81 d 1.24 1.65 e 0.64 f 0.10 0.25 g 0.38 1.27 h 0.18 0.25
0 8 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 129 september 22, 2011

24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.598 0.613 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013
0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 15.19 15.57 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33
0 8 rev. 1.30 130 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu

24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.335 0.346 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010
0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 8.51 8.79 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25
0 8 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 131 september 22, 2011

28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013
0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33
0 8 rev. 1.30 132 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu

28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010
0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25
0 8 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 133 september 22, 2011

44-pin qfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 0.528 b 0.390 0.398 c 0.512 0.528 d 0.390 0.398 e 0.031 f 0.012 g 0.075 0.087 h 0.106 i 0.010 0.020 j 0.029 0.037 k 0.004 0.008 l 0.004
0 7 symbol dimensions in mm min. nom. max. a 13.00 13.40 b 9.90 10.10 c 13.00 13.40 d 9.90 10.10 e 0.80 f 0.30 g 1.90 2.20 h 2.70 i 0.25 0.50 j 0.73 0.93 k 0.10 0.20 l 0.10
0 7 rev. 1.30 134 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu

reel dimensions ssop 16s (150mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 12.8 +0.3/-0.2 t2 reel thickness 18.2 0.2 sop 20w, sop 24w, sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2 0.2 sop 16n (150mil), ssop 20s (150mil), ssop 24s (150mil), ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2 0.2 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 135 september 22, 2011
carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.0 0.3 p cavity pitch 8.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 10.3 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 rev. 1.30 136 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
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ssop 16s symbol description dimensions in mm w carrier tape width 12.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 5.5 0.1 d perforation diameter 1.55 0.10 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.4 0.1 b0 cavity width 5.2 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 9.3 0.1 sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.8 0.1 b0 cavity width 13.3 0.1 k0 cavity depth 3.2 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 21.3 0.1 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 137 september 22, 2011
ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 9.0 0.1 k0 cavity depth 2.3 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 sop 24w symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.9 0.1 b0 cavity width 15.9 0.1 k0 cavity depth 3.1 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 21.3 0.1 rev. 1.30 138 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
ssop 24s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 9.5 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.10 b0 cavity width 18.34 0.10 k0 cavity depth 2.97 0.10 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 0.1 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu rev. 1.30 139 september 22, 2011
ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.0 0.3 p cavity pitch 8.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 10.3 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 rev. 1.30 140 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu
rev. 1.30 141 september 22, 2011 bs83b08-3/b12-3/b16-3/b16g-3/c24-3 8-bit touch key flash mcu copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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